The challenge of fault testing integrated logic circuits is becoming more formidable as advanced submicron processes for integrated circuit fabrication are developed. As is well known to those having skill in the art, an integrated logic circuit is an integrated circuit including large numbers of interconnected logic gates for accomplishing a predetermined logic function. Increased gate-count, higher integration densities, decreased relative I/O capability, smaller feature size, higher speeds, higher performance and increased complexity all severely restrict the application of conventional fault testing techniques in integrated logic circuits.
Although numerous techniques for transistor level fault modeling have been developed over the past years, most have not been widely used in integrated circuits because they either require excessive integrated circuit real estate, are not comprehensive in their range of fault detection, and/or cannot be consistently applied to a variety of circuit topologies and gate families. For example, many classes of logic circuits such as those designed using Complementary Metal Oxide Semiconductor (CMOS) processes, possess certain unique failure modes that cannot be adequately detected by conventional stuck-at, stuck-on or stuck-off modeling techniques. This is because these conventional techniques only test for extremes in device failure and do not recognize analog, intermediate and other types of failures that can cause signal degradation and delay. These latter types of failures are especially prevalent in advanced CMOS processes where process-induced defects commonly give rise to complex faults that are significantly different from those testable by conventional fault modeling techniques. Typical process related faults and a methodology for testing are described in an article by W. Maly, entitled "Realistic Fault Modeling for VLSI Testing," Design Automation Conference (1987), pp. 173-180.
In an article by R. L. Wadsack, entitled "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits," Bell System Technical Journal, (May-June 1978), pp. 1449-1473, conventional stuck-off testing techniques were used to detect catastrophic device failures caused when MOS and CMOS logic devices remained nonconducting in the presence of an applied turn-on bias. This type of fault is also known in the literature as a "stuck-open" fault. The converse of this type of failure is the "stuck-on" fault caused when a logic device remains conducting in the presence of a turn-off bias. Stuck-on types of faults also present a special testing problem since many of them remain undetectable using standard testing models.
A "stuck-at" fault measured at the higher gate level can be either a stuck-on or stuck-off fault. As well understood by one skilled in the art, a gate is generally made up of numerous transistors and is typically designed to perform a unique boolean function such as binary signal inversion (a NOT gate) or the NAND or NOR boolean logic functions. In older logic families, stuck-at fault modeling techniques covered most failure mechanisms, however, modern logic families can exhibit failures which cannot be detected with conventional stuck-at models. Such families include those fabricated using state-of-the-art MESFET, CMOS and other IGFET and bipolar families.
In recent years, spot defect modeling techniques have been developed as potential alternatives to stuck-at testing of logic gates fabricated using state-of-the-art processes such as CMOS. Spot defect modeling includes the development of a fault model based on circuit extraction from process level models containing topological and other fabrication layer aberrations. However, this approach fails to include the effects caused by material anomalies in the devices themselves. Other techniques such as current monitoring, commonly referred to as IDDQ testing, have also been proposed but are limited by the use of on-chip measurement structures which makes at-speed testing difficult and at best can only provide indirect measurement of device anomalies.
Other circuit designs for fault testing have mostly included techniques requiring the addition of transistors or the modification of the network topology to include test structures. At-speed testing has generally been avoided and much work has only involved stuck-on and stuck-off fault models. For example, in an article by S. M. Reddy and M. K. Reddy, entitled "Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits," IEEE Transactions on Computers, Vol. C-35, No. 8, (August 1986), pp. 742-754, it is shown that in a specific design using a single CMOS gate, single transistor stuck-open faults can be detected in the presence of arbitrary circuit delays. However, means for detecting intermediate faults wherein the transistor under test is neither stuck-on nor stuck-off is not disclosed.
Moreover, in an article by D. L. Liu and E. J. McCluskey, entitled "Designing CMOS Circuits for Switch Level Testability," IEEE Design and Test of Computers, (August 1987), pp. 42-49, a CMOS design for transistor level testability using a three pattern testing scheme to detect only stuck-on and stuck-off faults is described. Finally, in an article by S. Kundu and S. M. Reddy, entitled "On the Design of Robust Testable CMOS Combinational Logic Circuits," Eighteenth International Symposium on Fault-Tolerant Computing, Tokyo, Japan (June, 1988), pp. 220-225, a robust testing technique for detecting stuck-open faults and path delays is provided. The technique for detecting path delays is incapable of detecting intermediate faults in the transistors under test.
Patent protection has also been obtained for integrated circuits having means for detecting faulty transistors and, in particular, means for detecting "short channel" effects. For example, in U.S. Pat. No. 4,789,825, to Carelli et al., an integrated circuit having channel length indicator means is disclosed. The channel length indicator means includes a test transistor with a channel length substantially greater than that of the transistor under test. The purpose of the test transistor is to generate a reference voltage to which the output voltage of the transistor under test can be compared. An excessive difference in the respective voltages indicates the presence of short channel effects and gate independent operation. A signal flag is also generated to indicate the presence of the short channel. The disclosed integrated circuit does not, however, have means for detecting stuck-on, stuck-off, or intermediate faults in the transistor under test.
In summary, notwithstanding many attempts to provide complete fault detection at the transistor level, the various described stuck-at, delay fault, spot defect and IDDQ models only cover restricted subsets of the dominant failure mechanisms associated with modern integrated circuit technologies. Moreover, conventional fault detection techniques fail to detect many intermediate faults.